1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor device. The invention particularly relates to the method for manufacturing semiconductor device having a double-sided electrode structure (double-sided electrode package).
2. Description of the Related Art
Recently, three-dimensional package techniques with higher packaging density are being developed according to miniaturization of electronic devices such as mobile telephones. In the three-dimensional package techniques, a package-on-package (POP) method for laminating another package on one package is one of promising candidates. In POP, lamination of multi-layered packages having three or four layers is also proposed (see Japanese Patent Application Laid-Open (JP-A) No. 11-260999).
FIG. 18 illustrates a representative structure of conventional POP. In the POP structure, another package 2 is laminated on a package 1. In the lower package 1, semiconductor chips are connected in a flip-chip manner. The package 1 is provided with solder balls as connection terminals on its back surface side, and provided with a land portion obtained by applying solider paste to its surface side.
In the upper package 2, the semiconductor chips are connected by wire bonding, and are sealed by a resin. The package 2 is also provided with land portions as connection terminals on its back surface side. The land portions of the package 2 are provided at positions opposed to the package 1 in a laminated state. The land portions of the upper package 2 are electrically connected to the land portions of the lower package 1 by the solder balls 3.
However, the conventional POP has the following various problems, for example:
(1) since the packages are laminated, a mounting height should not be lower than a stack of semiconductor chips;
(2) when the packages are warped, electric connection reliability is deteriorated;
(3) since sealing of the lower package is not sufficient, moisture-resistant reliability is deteriorated; and
(4) since reduction in a diameter of the solder balls provided as the connection terminals onto the package is limited, the solder balls cannot cope with a multi-pin constitution of the semiconductor chips.
These problems arise from the structure of the packages to be laminated.
In the POP, a double-sided electrode package is used. The double-sided electrode package has at least an internal wiring to be connected to a semiconductor chip, a penetrating electrode which connects an electrode on a package surface side and the internal wiring, and another penetrating electrode which connects an electrode on a package back surface side and the internal wiring. In order to solve the problems of the conventional POP, a double-sided electrode package which has a structure with excellent reliability, productivity and general versatility should be developed.
The inventors propose a double-sided electrode package (semiconductor device) with a new structure which has a pillar-shaped surface-side terminal having plural protruded rims on an entire periphery of its side surface along a peripheral direction as a “penetrating electrode”. In this semiconductor device, adhesiveness between the surface-side terminal and a sealing resin is improved (see Japanese Patent Application Laid-Open (JP-A) No. 2009-004650). As a result, the device has an effect such that connection reliability and moisture-resistant reliability with respect to another package are excellent. JP-A No. 2009-004650 discloses a method for manufacturing the semiconductor device is a method for forming a sealing resin layer using a conventional resin sealing method such as a transfer molding method and grinding the sealing resin layer so as to expose one end of the surface-side terminal.